Advances in semiconductor manufacturing technologies have allowed circuit designers to continually improve the clock performance of high-speed logic devices including, but not limited to, microprocessors. Thus, microprocessor core clock speeds have continued to increase. However, partly due to the difficulty of increasing data bus speeds, systems having a plurality high speed logic devices interconnected through a data bus have not experienced the same degree of improved performance.
For purposes of discussion, FIG. 1 illustrates a system 10 comprising a data bus 12 electrically coupled to a plurality of high speed logic devices 14, 17, 19. Each logic device 14, 17, 19 is electrically coupled to the data bus 12 through an exemplary bus interface circuit 16. In order to coordinate the transfer of data between each of the logic devices 14, 17, 19, the system 10 may use a common-clock timing scheme and a source synchronous timing scheme, both of which are well known in the art. Typically, the common-clock timing scheme is the critical timing path, slowing the speed of data transfers between logic devices 14, 17, 19 and, therefore, the overall speed of the system 10.
The exemplary interface circuit 16 comprises a driver 20 and a receiver 22 electrically coupled to the data bus 12. The driver 20 is configured to receive a T13DATA signal from its corresponding logic device 14, 17, 19 and to transmit the T13DATA signal to the data bus 12. Typically, the T13DATA signal is latched to the driver 20 through a register 24 controlled by a clock signal BCK. The driver 20 may also be configured to transmit the T13DATA signal to the data bus 20 only upon receiving an ENABLE signal. Like the T13DATA signal, the ENABLE signal may be latched to the driver 20 through a register 26 controlled by the clock signal BCK. As used herein, the term xe2x80x9cdriving pathxe2x80x9d refers to the driver 20 and the registers 24, 26, collectively or individually. Similarly, the each of the registers 24 and 26 may be referred to as a xe2x80x9cdriving path registerxe2x80x9d. The receiver 22 is configured to receive an R13DATA signal from the data bus 12 and to transmit the R13DATA signal to a register 28. The receiving path register 28 is also configured to pass the R13DATA signal to its corresponding logic device 14, 17, 19. As used herein, the term xe2x80x9creceiving pathxe2x80x9d refers to the receiver 22 and the register 28, collectively or individually. Similarly the register 28 may be referred to as a xe2x80x9creceiving path registerxe2x80x9d.
In a common-clock timing scheme, a single clock is shared by the driving and receiving elements coupled to a data bus. As shown in FIG. 1, each exemplary interface circuit 16 employs a common-clock timing scheme wherein the driving path registers 24, 26 and the receiving path registers 28 are controlled by the same clock signal BCK. Sharing the clock signal BCK between the driving path registers 24, 26 and the receiving path registers 28 places a theoretical limit on the maximum frequency at which the common-clock data bus 12 can operate. The limitation stems from the total delay introduced between a driving path and a receiving path of the interface circuits 16.
To illustrate the maximum frequency limitation, FIG. 2 shows a timing diagram with two clock signals, BCK (slower) and BCK (faster), having different periods. FIG. 2 also shows a time line illustrating the times when a bit of data of the T13DATA signal is driven by a driver 20 and received by a receiver 22 in relation to the two clock signals. The elapsed time between the time when the bit is driven and the time when it is received is referred to herein as the xe2x80x9ctotal delayxe2x80x9d or xe2x80x9ctotal delay timexe2x80x9d of the signal. The driving path registers 24, 26 are configured to pass the a bit to the driver 20 upon a first positive transition of the clock signal BCK (slower) and the receiving path register 28 is configured to latch in the bit from the receiver 22 upon a second positive transition of the clock signal BCK (slower). To ensure correct latching, the receiver 22 may be configured with setup and hold requirements that define the minimum times that the received bit must be held in the receiving path register 28 before and after a positive transition of the clock signal BCK (slower).
One skilled in the art will recognize that the bit driven at the first positive transition of the clock signal BCK (slower) must be received at the receiver before the second transition of the clock signal BCK (slower) in order to be latched into the receiving path register 28 correctly. Otherwise, a subsequent bit may be received at the receiver 22 before the bit is latched into the receiving path register 28 or a previous bit may be latched into the receiving path register 28 more than once. As used herein, the term xe2x80x9cracexe2x80x9d refers to the condition wherein a first bit is received at the receiver 22 but is not latched into the receiving path register 28 before a second bit is received at the receiver 22. Thus, the total delay must remain less than the delay of one cycle of the clock signal BCK (slower). As shown in the example in FIG. 2, this requirement is met. However, if the registers 24, 26, 28 of FIG. 1 are controlled by the higher frequency clock signal BCK (faster), the total delay may be greater than the delay of one cycle of the clock signal BCK (faster), causing race or other timing problems. Therefore, the maximum frequency at which the common-clock data bus 12 can operate is limited to clock signals having periods greater than the total delay.
Referring again to FIG. 1, to design a common-clock data bus 12, each factor contributing to the total delay must be accounted for to determine a common-clock timing budget, or minimum allowable cycle for the clock signal BCK. The total delay of the T13DATA signal comprises the sum of the delays introduced by each element of the system through which the T13DATA signal passes. Thus, a T13DATA signal passing through fewer system elements will have less total delay than a T13DATA signal passing through more system elements. For example, the total delay of a T13DATA signal communicated between the driver 20 and the receiver 22 of the same logic device, such as logic device 14, may include delays introduced by the driving path registers 24, 26, the driver 20, the receiver 22, and the receiving path register 28 of logic device 14. However, the total delay of a T13DATA signal communicated between logic device 14 and logic device 17 may include delays introduced by the driving path registers 24, 26 and the driver 20 of logic device 14, the packaging (not shown) of logic device 14, the length of printed circuit board traces (not shown) of the data bus 12, the packaging (not shown) of logic device 17, and the receiver 22 and receiving path register 28 of logic device 17. Further, due to the delay introduced by the length of the printed circuit board traces of the data bus 12, logic devices 14, 17, 19 that are the farthest away from each other on the data bus 12 will experience the greatest delay when communicating a T13DATA signal between each other.
Once the common-clock timing budget is determined, it may be desirable to increase the maximum frequency at which the common-clock data bus 12 can operate by decreasing the total delay time along any given communication path. Thus, it may be advantageous to shorten the length of printed circuit board traces in the data bus 12 or to shorten packaging leads. However, the amount of delay eliminated from such measures may be minimal. It may also be advantageous to reduce the propagation delays of the registers 24, 26, 28, the drivers 20, and the receivers 22 in FIG. 1 by decreasing their switching times (e.g., reducing the finite delay between the application of an input pulse and an output response). However, reducing propagation delays may create noise problems due to the high frequencies associated with slew rates.
The present disclosure relates to increasing the speed of a common-clock data bus. An interface circuit configured to drive and receive data on a data bus according to an exemplary embodiment includes a common-clock provided to a driving path and a receiving path of the interface circuit and time borrowing circuitry electrically coupled to the receiving path. The time borrowing circuitry is configured to dynamically delay the common-clock before it is provided to the receiving path. In another embodiment, the time borrowing circuitry is configured to selectively provide the common-clock or the dynamically delayed common-clock to the receiving path. The time borrowing circuitry may be configured to provide the common clock, rather than the dynamically delayed common-clock, to the receiving path when the driving path is driving data onto the data bus. In yet another embodiment, the time borrowing circuitry is configured to selectively switch between providing the common-clock or the dynamically delayed common-clock only at select time intervals.
In another embodiment, the interface circuit comprises at least one driving path register coupled to a driver, a receiving path register coupled to a receiver, and a delay line coupled between a common-clock signal and a clock input of the receiving path register. The interface circuit may further comprise a multiplexer having an output coupled to the clock input of the receiving path register, the multiplexer configured to switch its output between the common-clock and the output of the delay line. The interface may further comprise a NOR gate electrically coupled to the common-clock and the output of the delay line and a latch electrically coupled to the output of the NOR gate. The NOR gate and latch may be configured to provide a signal to the multiplexer only when the common-clock and the output of the delay line are both at a low logic level.
A logic device according to another embodiment comprises an interface circuit including a driving path, a receiving path, and time borrowing circuitry. The time borrowing circuitry may be configured to dynamically delay a common-clock signal provided to the receiving path. A system according to another embodiment comprises a plurality of logic devices electrically coupled to a data bus, each logic device comprising a driving path, a receiving path, and a time borrowing circuitry. The time borrowing circuitry may be configured to provide a common-clock to the receiving path when a driving path of an external logic device is driving and to provide a dynamically delayed version of the common-clock signal to the receiving path when the driving path within the same logic device is driving.
Other features and advantages will become apparent to those of skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.